◾ 서울대학교 전기정보공학부 박사 (2025)
◾ 서울대학교 전기정보공학부 석사 (2020, 삼성전자 학술연수)
◾ 고려대학교 전기전자전파공학부 학사 (2012)

◾ 서울과학기술대학교 전기정보공학과 조교수 (2025. 09.~현재)
◾ 서울대학교 반도체공동연구소 박사후연구원 (2025. 03.~2025. 08.)
◾ 삼성전자 DS부문 반도체연구소 책임연구원 (2012. 01.~2021. 03.)

◾ 차세대 반도체 회로 설계
◾ 인공지능 가속기 회로 설계

￭ Ferroelectric Field-Effect Transistor Synaptic Device with Hafnium-Silicate Interlayer, IEEE Electron Device Letters, vol. 44, No. 12, pp. 1955~1958, Dec. 2023.
￭ Efficient Convolutional Processing of Spiking Neural Network with Weight-Sharing Filters, IEEE Electron Device Letters, vol. 44, No. 6, pp. 1007~1010, Jun. 2023.
￭ Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application, IEEE Journal of the Electron Devices Society, vol. 11, pp. 95~100, Jan. 2023.
￭ Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap, IEEE Transactions on Nanotechnology, vol. 21, pp. 534~538, Sep. 2022.
￭ Spiking Neural Network with Weight-Sharing Synaptic Array for Multi-input Processing, IEEE Electron Device Letters, vol. 43, No. 10, pp. 1657~1660, Aug. 2022.
￭ Novel Dual Liner Process for Side-Shielded Forksheet Device with Superior Design Margin, IEEE Transactions on Electron Devices, vol. 69, No. 5, pp. 2232–2235, May 2022.
￭ Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond, IEEE Transactions on Electron Devices, vol. 69, No. 4, pp. 2088~2093, Apr. 2022.
￭ Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory, IEEE Transactions on Electron Devices, vol. 69, No. 3, pp. 1048~1053, Mar. 2022.
￭ Suppression of Statistical Variability in Stacked Nanosheet Using Floating Fin Structure, IEEE Electron Device Letters, vol. 42, No. 11, pp. 1580~1583, Nov. 2021.
￭ Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory, IEEE Electron Device Letters, vol. 42, No. 11, pp. 1607~1610, Nov. 2021.
￭ Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs, IEEE Transactions on Electron Devices, vol. 67, No. 6, pp. 2648~2652, Jun. 2020.
￭ Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure, IEEE Transactions on Electron Devices, vol. 67, No. 4, pp. 1859~1863, Apr. 2020.
￭ Negative Capacitance Effect on MOS Structure: Influence of Electric Field Variation, IEEE Transactions on Nanotechnology, vol. 19, pp. 168~171, Feb. 2020.
￭ Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET from OFF-State Leakage Perspective, IEEE Transactions on Electron Devices, vol. 67, No. 3, pp. 1317~1322, Mar. 2020.
￭ Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique, Solid-State Electronics, vol. 164, No. 107701, Fab. 2020.

￭ Compute-in-Memory Array Design using Stacked Hybrid IGZO/Si eDRAM cells, ACM/IEEE Design, Automation and Test in Europe Conference (DATE), Mar. 2025 (BK21우수학회, Nominated as Best Paper Awards).
￭ 4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO/Si Transistors, ACM/IEEE Design Automation Conference (DAC), Nov. 2024 (BK21 우수학회).
￭ Analysis on Endurance Characteristics of Ferroelectric Memory Device, IEIE International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 630–633, Jul. 2022.
￭ Novel Stacked Floating Fin Structure Gate-All-Around Field-Effect Transistor for Design and Power Optimization, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), pp. 136–138, Mar. 2019.
￭ Accurate Effective Width Extraction Methods for Sub-lOnm Multi-Gate MOSFETs through Capacitance Measurement, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), pp. 115–117, Mar. 2019.
￭ Analysis on Fully Depleted Negative Capacitance Field-Effect Transistor (NCFET) Based on Electrostatic Potential Difference, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), pp. 422–424, Mar. 2019.

￭ Methods of manufacturing a semiconductor device using a mask, US12225703B2, United States Patent (등록), Fab. 2025.
￭ Semiconductor device and method of fabricating the same where semiconductor device includes high-k dielectric layer that does not extend between inhibition layer and side of gate electrode, US12199163B2, United States Patent (등록), Jan. 2025.
￭ Semiconductor device, US12191368B2, United States Patent (등록), Jan. 2025.
￭ Semiconductor devices and methods for fabricating the same, US11973111B2, United States Patent (등록), Apr. 2024.
￭ Semiconductor devices and methods for fabricating the same, US11908861B2, United States Patent (등록), Fab. 2024.
￭ Semiconductor device, US11832430B2, United States Patent (등록), Nov. 2023.
￭ Semiconductor device and method of fabricating the same, US11804530B2, United States Patent (등록), Oct. 2023.
￭ Semiconductor devices having multi-channel active regions and methods of forming same, US11798949B2, United States Patent (등록), Oct. 2023.
￭ Semiconductor device, US11749678B2, United States Patent (등록), Sep. 2023.
￭ Semiconductor device including non-sacrificial gate spacers and method of fabricating the same, US11705503B2, United States Patent (등록), Jul. 2023.
￭ Semiconductor devices including a narrow active pattern, US11482522B2, United States Patent (등록), Oct. 2022.
￭ Semiconductor devices including a narrow active pattern, US11404412B2, United States Patent (등록), Aug. 2022.
￭ Semiconductor devices having multi-channel active regions and methods of forming same, US11329066B2, United States Patent (등록), May 2022.
￭ Semiconductor devices having a fin-shaped active region and methods of manufacturing the same, US11257925B2, United States Patent (등록), Feb. 2022.
￭ Integrated circuit device, US10396205B2, United States Patent (등록), Aug. 2019.
￭ Semiconductor devices and inverter having the same, US9966376B2, United States Patent (등록), May 2018.
￭ Semiconductor device having first and second gate electrodes and method of manufacturing the same, US9576959B1, United States Patent (등록), Feb. 2017.
￭ Semiconductor devices including contact patterns having a rising portion and a recessed portion, US9536968B2, United States Patent (등록), Jan. 2017.
￭ Semiconductor device, US9331199B2, United States Patent (등록), May 2016.
￭ 랜덤 액세스 메모리 및 그 제조 방법, 10-2755896, 대한민국 특허 (등록), Jan. 2025.
￭ 랜덤 액세스 메모리 및 그 제조 방법, 10-2730001, 대한민국 특허 (등록), Nov. 2024.
￭ 스파이크 신호를 병렬처리하는 뉴로모픽 장치, 10-2514655, 대한민국 특허 (등록), Mar. 2023.